IP Cores, Inc. Delivers a 10 Gbps AES-GCM FPGA Implementation

IP Cores, Inc. announces an FPGA implementation of the AES Galois/Counter Mode (GCM) supporting the IEEE 802.1ae standard with real-life throughput exceeding 10 Gbps for all Ethernet frame sizes.

Palo Alto, California, June 12, 2007 -- IP Cores, Inc. demonstrated the high throughput of its AES-GCM solutions by delivering an FPGA implementation of its GCM3 core that provides true 10 Gbps throughput for 10G Ethernet equipment for all Ethernet frame sizes.

"Delivery of a true 10 Gbps GCM3 core demonstrates our commitment to the high-speed FPGA implementations," said Dmitri Varsanofiev, CTO of IP Cores. "High-speed Ethernet equipment can now easily implement the line-speed IEEE 802.1ae encryption in an FPGA."

Line-speed Ethernet Encryption Standard Support

The IEEE 802.1ae encryption standard uses the Advanced Encryption Standard (AES) in the Galois/counter mode (GCM). For most Ethernet application, maintaining the line-speed throughput for all frame sizes is essential.

IP Cores, Inc. has designed the GCM2 and GCM3 families of the AES-GCM cores to maintain full-speed throughput for all Ethernet frame sizes. This allowed the cores to reliably deliver a line-speed 10 Gbps throughput using a Xilinx Vrtex-4 FPGA even for the shortest Ethernet frames. The ASIC implementations of the same cores deliver throughputs of 70 Gbps and beyond.

GCM2 family of cores core is optimized to handle 128-bit keys, while GCM3 supports 128, 192, and 256 bit AES keys. Cores are available in multiple configurations to meet specific SoC throughput, power, and gate count goals. Gate count for a fully self-contained GCM2 or GCM3 core starts at 30K ASIC gates.  For more information about IP Cores’ product line, please visit www.ipcores.com.

About IP Cores, Inc.
IP Cores is a rapidly growing company in the field of security IP cores. Founded 3 years ago, the company provides IP cores for encryption of communications and storage data.