IP Cores, Inc. Ships a Multi-Gigabit Combo AES/XTS, AES/CBC and AES/GCM IP Core

IP Cores, Inc. Ships a Multi-Gigabit Combo AES/XTS, AES/CBC and AES/GCM IP Core for Attached Storage Applications

IP Cores, Inc. has shipped a silicon IP core supporting storage and networking security standards. Starting at 70K ASIC gates and delivering over 10 Gbps throughput, GXC3 cores provides a compact and efficient solution for an SoC designer working on a secure IEEE P1619 storage and IEEE 802.1AE networking solutions.

Palo Alto, California, November 5, 2007 -- IP Cores, Inc. today announced shipment of a new silicon IP core supporting the IEEE P1619 storage encryption standard, IEEE 802.1AE MACsec network data encryption standard, and legacy storage AES/CBC encryption. The new GXC3 core enables System on Chip (SoC) vendors to build compact cryptographic processors that support the AES/XTS, AES/GCM, and AES/CBC cryptographic algorithms.

"A modification of our popular GXM3 core, the GXC3 core adds support for the legacy AES/CBC encryption and decryption mode without any insignificant increase in size. With the shipment of the GXC3 combo core we enabled our customers to add the support for legacy encryption to their secure storage designs," said Dmitri Varsanofiev, CTO of IP Cores, Inc. "Our lead customers had converted their early access to GXC3 into a competitive advantage for their networked storage solutions."

High-speed Encryption Protects Data in Storage and inside the Network
Advanced Encryption Standard (AES) is widely used to provide data security in storage, both “at rest” on a hard drive or tape and on the network. Addressing the market demand for integrated high-speed AES crypto solutions for these two markets, IP Cores’ GXC3 supports the XTS-AES, GCM-AES, and CBC-AES modes in a single core. GXC3 supports 128-bit and 256-bit AES keys for design flexibility and is designed for throughput of 18.2 Mbits per MHz for a maximum throughput of 10 Gbps at 550 MHz clock frequency.

XEX-based Tweaked CodeBook mode (TCB) with CipherText Stealing (CTS) - abbreviated as XTS - mode of AES is a highly parallelizable mode used in the IEEE standard P1619 for narrow-block hard disk encryption. GXC3 also includes the Galois/Counter Mode (GCM) cipher designed to provide data security and authentication, and a support for the legacy tape and disk encryption Cipher Block Chaining (CBC) mode. AES in GCM mode allows parallel authentication implementations and therefore can be used for communication channels that require very high-speed authenticated encryption, such as supporting IEEE 802.1AE MACsec security for Ethernet networks, or IPsec RFC 4106. GXC3 configurations support AES/GCM, AES/CBC and AES/XTS encryption and decryption throughput over 10 Gbps in a single core, with easy parallelization for higher throughputs. Gate count for a fully self-contained GXC3 starts at 70K gates.

GXC3 contributes to the IP Cores’ efficient portfolio of AES-based security IP cores that includes support for AES and DES ECB, CTR, OFB, CFB modes, GCM-AES, XTS-AES, LRW-AES, and a set of AES-CCM implementations for a variety of telecommunications security standards (IEEE 802.11i Wi-Fi, 802.16e WiMAX, 802.15.3 UWB WiMedia, and 802.15.4 Zigbee). For networking and storage applications requiring much higher throughputs (40 Gbps, 100 Gbps and above), IP Cores, Inc. offers dedicated GCM and XTS core families. IP Cores, Inc. has also shipped a family of FFT DSP cores. Cores are available in multiple configurations to meet specific SoC throughput, power, and gate count goals. For more information about IP Cores’ product line, please visit www.ipcores.com.

About IP Cores, Inc.
IP Cores is a fast-moving company in the field of security and DSP IP cores. Founded 3 years ago, the company provides IP cores to protect communications, storage, and intellectual property.