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Ultra-Compact Advanced Encryption Standard (AES) Core
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General Description
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Base Core Features
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The AES core implements
Rijndael cipher encoding and decoding in compliance with the
NIST Advanced Encryption Standard. It processes 128-bit
data blocks with 128-bit key (a 256-bit key version is
available).
Basic core is designed only for encryption and is the
smallest available on the market (less than 3,000 gates). Enhanced versions are
available that support encryption and decryption for
various cipher modes (ECB,CBC, OFB, CFB, CTR), as well
as different datapath widths for size/performance tradeoff. The
core includes the key expansion logic.
The design is fully synchronous and available in both
source and netlist form. |
Encrypts using the AES Rijndael Block Cipher Algorithm.
Satisfies Federal Information Processing Standard
(FIPS) Publication 197 from the US National Institute
of Standards and Technology (NIST). FIPS-197
validated.
Processes 128-bit data blocks with 8, 16 or 32-bit
data interface
Employs key sizes of 128 bits (AES128), 192, or 256
bits (AES256)
Includes the key expansion function
Optional parity check feature
Simple, fully synchronous, reusable design
Completely self-contained: does not require external
memory
Available as fully functional and synthesizable Verilog,
or as a netlist for popular programmable devices and ASIC libraries
Deliverables include test benches
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Symbol
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Applications
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- Cipher for wireless communications, including
IEEE 802.11i, IEEE 802.15.3, IEEE 802.15.4 (Zigbee), MBOA,802.16e,
Wibree, sensor networks ("smart dust"), motes
- Electronic financial transactions
- Power line networks
- Digital Rights Management (DRM)
- Secure video surveillance systems
- Encrypted data storage
- Secure RFID, immobilizers
- Secure Smart Cards
- ITU H.235 VoIP encryption
- Secure RTP (SRTP, RFC 3711)
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Pin Description
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Name
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Type
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Description
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CLK
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Input
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Core
clock signal |
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EN
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Input
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Synchronous
enable signal. When LOW the core ignores all its inputs
and all its outputs must be ignored. |
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START
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Input
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When
goes HIGH, a cryptographic operation is started |
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LOAD
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Output
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Input
data request signal |
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READY
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Output
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Output
data ready and valid |
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8-bit Data Interface
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KEY[7:0]
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Input
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Encryption
Key |
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PT[7:0]
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Input
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Input
Plain Text Data |
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CT[7:0]
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Output
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Output
Cipher Text Data |
| 16-bit
Data Interface |
| KEY[15:0] |
Input |
Encryption
Key |
| PT[15:0] |
Input |
Input
Plain Text Data |
| CT[15:0] |
Output |
Output
Cipher Text Data |
| 32-bit
Data Interface |
| KEY[31:0] |
Input |
Encryption
Key |
| PT[31:0] |
Input |
Input
Plain Text Data |
| CT[31:0] |
Output |
Output
Cipher Text Data |
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Function Description
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An AES encryption operation transforms a 128-bit
block into a block of the same size. The encryption key size
is 128 bit. The key is expanded during cryptographic operations.
The block performs AES encryption as defined in the FIPS-197
http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
and SP 800-38A
http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf
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Operation
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| A rising input on the START port triggers the
beginning of a cryptographic operation on the data PT, using
the KEY as key. The core then raises the LOAD signal requesting
the data block. It then starts to process the state according
to the AES algorithm. The timing diagram below shows how the
data is fed to the core at the start. |
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Key and data input at the start
of encryption
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Both the data and the key are input serially,
8, 16 or 32 bits at the time. The diagram above shows the
case where the input data is 8 bit
When all the rounds are completed, the READY signal is raised
and the encrypted data starts to flow out. This is shown in
the timing diagram below. |
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Cipher text output
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It is possible to start a new cryptographic operation
as soon as the data from the previous one is output. A cryptographic
operation can be aborted at any time by lowering the START
signal for at least one clock cycle.
The core is fully pipelined. Keeping the START signal HIGH
causes the new cryptographic operation to start simultaneously
with ending of previous one; in this case LOAD and READY signals
are generated by the core simultaneously. Loading of the new
plain text data and key is combined with outputting cipher
text data from |
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| the previous operation. This is shown in the
timing diagram below. |
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Cipher text from a previous operation
is being output while new plaintext is input
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New key can be used for each cryptographic operation. The
absence of gaps allows sustaining the throughput listed in
the table below. |
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Core
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AES1-8
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AES1-16
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AES1-32
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AES1-64
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AES1-128 |
| Cycles
for 128-bit key |
160
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80
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40
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20
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10 |
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Bit per clock cycle
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12.8 |
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Synthesis Details
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| The core size starts at less than 3K ASIC
gates. The 128-bit wide core has been synthesized in the
TSMC 90 nm LV process to run at above 800 MHz, delivering 10
Gbps of throughput. Representative area/resources figures are shown below. |
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Core |
Technology
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Area / Resources
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Throughput
bits / clock |
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AES1-8E |
TSMC 0.18 u
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2948 gates
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0.8 |
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AES1-8E |
Altera FPGA
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639 ALUT
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0.8 |
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AES1-8E |
Actel ProAsic-3
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864 tiles
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0.8 |
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AES1-8E |
Actel RTAX2000 |
3386 cells |
0.8 |
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AES1-32E/256 |
Xilinx FPGA
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284 slices
7 BRAM
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3.2 |
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AES1-32CBCE |
Actel A3P400 |
18% |
3.2 |
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AES1-32CBC |
Altera FPGA |
718 ALUT
24576 bits |
3.2 |
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Please feel free to contact us
for additional synthesis data.
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Available Versions
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| The AES core is available in AES-ECB, AES-CFB,
AES-CBC, AES-OFB, AES-OMAC
and AES-CTR modes, for different data path widths, and for key
sizes of 128, 192, and 256 bits. Encryption- and decryption-only
options are also available (identified by E/D). The core
is name is formed in the following way: AES1-<internal
width>[/<external data bus width>][mode][E/D][/key size]. By
default the data bus width is equal to the internal core
width, mode is ECB, core is E+D, and the key size is 128
bits. For example, AES1-32E/256 is an ECB encryption-only
32-bit wide core supporting 256-bit keys, AES1-32CBC is an AES
core implementing the AES-CBC mode. |
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Export Permits
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US Bureau of Industry and Security has assigned
the export control classification number 5E002 to the core.
The core is eligible for the license exception ENC under section
740.17(A) and (B)(1) of the export administration regulations.
See the licensing basics page,
for links to US government sites and more details. |
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Deliverables
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HDL Source Licenses
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Netlist Licenses
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- Synthesizable Verilog RTL source code
- Testbench (self-checking)
- Test vectors
- Expected results
- Simulation script
- Synthesis script
- User Documentation
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- Post-synthesis EDIF
- Testbench (self-checking)
- Test vectors
- Expected results
- Place & Route script
- Simulation script
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- NIST FIPS-197 certification (AESAVS) test bench is
available as an option
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Contact Information
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