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General Description

Implementation of the new WPAN security standard for MBOA MAC requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and message authentication. The CCM3M AES core is tuned for MBOA MAC applications and as such requires much smaller gate count than a full implementation. The core contains the base AES core AES1 and is available for immediate licensing.
The design is fully synchronous and available in both source and netlist form.

Key Features

Small size: From 9,500 ASIC gates at MBOA data speeds
Completely self-contained: does not require external memory
Includes encryption, decryption, key expansion and data interface
Support for Counter Mode Encryption (CTR) operation and CCM extensions (Counter Mode with CBC MAC)
Automatic generation of key context from key data
Flow-through design
Test bench provided
Pin Description
CLK Input   Core clock signal
CEN Input   Synchronous enable signal. When LOW the core ignores all   its inputs and all its outputs must be ignored.
MODE Input   Mode. When HIGH, transmit, when LOW receive
START Input   HIGH starting input data processing
READ Output   Read request for the input data byte
DATA_VALID Input   HIGH when valid data byte present on the input
WRITE output   Write to the output interface
OUT_READY Input   HIGH when output interface is ready to accept data byte
D[ ] Input   Input Data
Q[ ] Output   Output Data
DONE Output   Data processing completed
Function Description
The Advanced Encryption Standard (AES) algorithm is a new NIST data encryption standard as defined in the http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf

The WPA2 implementation fully supports the AES algorithm for 128 bit keys in Counter Mode (CTR) method of encryption with CBC message integrity check as required by the CCM protocol of the 802.11i standard.

The core is designed for flow-through operation, with byte-wide input and output interfaces. CCM6 key and nonce material precedes the frame in the flow of data. WPA2 supports encrypt and decrypt modes

Implementation Results
Device Utilization and Performance

Representative area/resources figures are shown below.

TSMC 0.18 u 9500 gates
Export Permits
US Bureau of Industry and Security has assigned the export control classification number 5E002 to our AES core. The core is eligible for the license exception ENC under section 740.17(A) and (B)(1) of the export administration regulations. See the licensing basics page, for links to US government sites and more details.

HDL Source Licenses

Synthesizable Verilog RTL source code
Test bench (self-checking)
vectors for testbenches
Expected results
Simulation script
Synthesis script
User Documentation

Netlist Licenses

Post-synthesis EDIF
Testbench (self-checking)
vectors for testbenches
Expected results
Place & Route script
Simulation script
Contact Information
IP Cores, Inc.
3731 Middlefield Rd.
Palo Alto, CA 94303, USA
Phone: +1 (650) 815-7996
E-mail: info@ipcores.com