Overview
LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encoding schemes used in the ITU G.9960 standard..
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Design Features
- Technology Independent
- Fully Synchronous Design
- Highly Modular Design with clearly defined interfaces
- Scan friendly RTL
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Key Features
- parameterized input data width 5-8 bit
- parameterized internal data width 7-12 bit
- nearly floating point performance with quantization of 6 input bits and internal computation in 10 bits (less than 0.3 dB from floating point BP with 50 iterations);
- early stop detection unit ;
- bit-LLR input
- Decoder throughput with 10 iterations at 400 MHz clock frequency is listed in the Table 1 below
- Decoder area:
240K gates 224 DPRAM 128x16 128 DPRAM 32x16 48 ROM 16x64
- Encoder area:
40K gates
40 Kbit DPRAM
50 Kbit ROM
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