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RSA5X Core
Scalable RSA and Elliptic Curve Accelerator Core

General Description

Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. The operations necessary for the RSA cannot be efficiently implemented on an embedded CPU, typically requiring many seconds of the CPU time for signature verification.

RSA5X implements by far the most time-consuming operation of the RSA cryptography: so called “exponentiation” to enable low-power operation of the battery-powered devices.

RSA5X also can perform addition and multiplication in the GF(p) and GF(2n) Galois fields under microprogram control, allowing for flexible elliptic curve cryptography (ECC) calculation on arbitrary curves..

The design is fully synchronous and available in multiple configurations varying in bus widths and throughput.


Key Features

  • Small size: RSA5X starts from less than 15K ASIC gates (size greatly depends on the core configuration)
  • Implements the computationally demanding parts of RSA public key cryptography for long life battery powered applications
  • Support for RSA with programmable bit sizes
  • Support for addition and multiplication in GF(p) and GF(2n) with programmable size
  • Microprogramming support for elliptic curve algorithms
  • Microprocessor-friendly interface using external dedicated memory for arguments, results, and scratch storage.
  • An option to share the memory with the microprocessor is available.
  • Test bench provided



  • Secure communications systems
  • Digital Rights Management (DRM) for battery powered electronics
  • Digital Signature using Reversible Public Key (rDSA) standard ANSI X9.31
  • Digital Signature Standard (DSS) FIPS-186
  • PKCS RSA cryptography per RFC 2347
  • High performance RSA accelerators
  • Elliptic curve cryptography per FIPS 186-3, NIST SP800-56A, SEC 1 and SEC 2 standards

Pin Description

Name Type Description
CLK Input Core clock signal
reset Input HIGH level asynchronously resets the core
Din[ ] Input Core input data
Dout[ ] Output Core output data
A[ ] Input Address for the core memory or on-chip registers
read Input Core read request
write Input Core write request
memDin[ ] Input Dedicated external memory input data (two ports for dual-port memory)
memDout[ ] Output Dedicated external memory output data (two ports for dual-port memory)
memA[ ] Output Address for the dedicated external memory (two ports for dual-port memory)
oe Output Output enable request for the dedicated external memory (two pins for dual-port memory)
we Output Write enable for the dedicated external memory (two pins for dual-port memory)
done Output HIGH level indicates a completion of computation

Function Description

The core implements the exponentiation operation of the RSA cryptography Q = Pk. The operands for the exponentiation: k and P as well as the modulus are programmed into the memory and the calculation is started. Once the operation is complete, the result Q can be read through the interface.

The core supports elliptic curve calculations through a flexible microprogram interface.



The core comes in a variety of options:

  • Throughput options (-1, -2, -3, etc). Bigger number corresponds to higher throughput. RSA5X is designed for low-medium throughput (tens to hundreds or RSA operations per second)
  • Use of 16-bit or 32-bit slice processing
  • Optional support for binary elliptic curves