IP Cores, Inc. announces shipment of silicon IP cores supporting the security standards FIPS-197, IEEE 802.1AE and P1619.1 for Actel FPGA devices. Starting at 800 tiles for AES1-8E and delivering 11.2 Mbps on RTSX radiation-tolerant devices, AES and AES/GCM cores provide a compact and high-performance solution for an FPGA designer working on a secure communication solution.

Palo Alto, California, June 17, 2008 -- IP Cores, Inc., setting the new benchmark for security IP cores, had shipped AES and AES/GCM IP cores supporting the FIPS-197, IEEE 802.1AE and P1619.1 standards. AES1 and GCM1 IP cores enable FPGA vendors to add encryption to their designs utilizing less than 15% of the RT54SX72S device.

"AES1-8 and GCM1-8 cores are ideally suited for security implementations that fit into compact low-power, rad-hard and rad-tolerant devices," said Dmitri Varsanofiev, CTO of IP Cores. "Our cores enable customers to implement encryption designs with data rates in the range of 10 Mbps to more than 400 Mbps utilizing just a small fraction of a typical Actel FPGA."

AES and AES/GCM Encryption Supports Secure Communications
Advanced Encryption Standard in Galois/Counter Mode (GCM-AES) is used the IEEE standards 802.1AE for layer 2 transport security and P1619.1 for tape encryption. Addressing the market demand for ultra-compact AES crypto solutions for Actel FPAG market, IP Cores had shipped its AES1 and GCM1 cores targeted for RTSX, ProASIC, ProASIC3, IGLOO, and ProASIC Plus APA FPGA families.

AES1 and GCM1 configurations support AES and AES/GCM encryption and decryption respectively with throughputs exceeding 100 Mbps in a single core. IP Cores’ expanding portfolio of security and DSP IP cores includes AES and AES/GCM cores available in multiple configurations to meet specific throughput, power, and FPGA resource utilization targets. For more information about IP Cores’ product line, please visit www.ipcores.com. Descriptions of the GCM-AES cores are available at http://ipcores.com/MACsec-802.1AE-AES-GCM-Core.htm.

About IP Cores, Inc.
IP Cores is a rapidly growing company in the field of security and DSP IP cores. Founded 4 years ago, the company provides IP cores for communications and storage fields, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), cryptographically secure pseudo-random number generators (CS PRNG), low-latency fixed and floating-point FFT and IFFT cores.

IP Cores, Inc. has shipped a silicon IP core supporting storage and networking security standards. Starting at 70K ASIC gates and delivering over 10 Gbps throughput, GXC3 cores provides a compact and efficient solution for an SoC designer working on a secure IEEE P1619 storage and IEEE 802.1AE networking solutions.

Palo Alto, California, November 5, 2007 -- IP Cores, Inc. today announced shipment of a new silicon IP core supporting the IEEE P1619 storage encryption standard, IEEE 802.1AE MACsec network data encryption standard, and legacy storage AES/CBC encryption. The new GXC3 core enables System on Chip (SoC) vendors to build compact cryptographic processors that support the AES/XTS, AES/GCM, and AES/CBC cryptographic algorithms.

"A modification of our popular GXM3 core, the GXC3 core adds support for the legacy AES/CBC encryption and decryption mode without any insignificant increase in size. With the shipment of the GXC3 combo core we enabled our customers to add the support for legacy encryption to their secure storage designs," said Dmitri Varsanofiev, CTO of IP Cores, Inc. "Our lead customers had converted their early access to GXC3 into a competitive advantage for their networked storage solutions."

High-speed Encryption Protects Data in Storage and inside the Network
Advanced Encryption Standard (AES) is widely used to provide data security in storage, both “at rest” on a hard drive or tape and on the network. Addressing the market demand for integrated high-speed AES crypto solutions for these two markets, IP Cores’ GXC3 supports the XTS-AES, GCM-AES, and CBC-AES modes in a single core. GXC3 supports 128-bit and 256-bit AES keys for design flexibility and is designed for throughput of 18.2 Mbits per MHz for a maximum throughput of 10 Gbps at 550 MHz clock frequency.

XEX-based Tweaked CodeBook mode (TCB) with CipherText Stealing (CTS) - abbreviated as XTS - mode of AES is a highly parallelizable mode used in the IEEE standard P1619 for narrow-block hard disk encryption. GXC3 also includes the Galois/Counter Mode (GCM) cipher designed to provide data security and authentication, and a support for the legacy tape and disk encryption Cipher Block Chaining (CBC) mode. AES in GCM mode allows parallel authentication implementations and therefore can be used for communication channels that require very high-speed authenticated encryption, such as supporting IEEE 802.1AE MACsec security for Ethernet networks, or IPsec RFC 4106. GXC3 configurations support AES/GCM, AES/CBC and AES/XTS encryption and decryption throughput over 10 Gbps in a single core, with easy parallelization for higher throughputs. Gate count for a fully self-contained GXC3 starts at 70K gates.

GXC3 contributes to the IP Cores’ efficient portfolio of AES-based security IP cores that includes support for AES and DES ECB, CTR, OFB, CFB modes, GCM-AES, XTS-AES, LRW-AES, and a set of AES-CCM implementations for a variety of telecommunications security standards (IEEE 802.11i Wi-Fi, 802.16e WiMAX, 802.15.3 UWB WiMedia, and 802.15.4 Zigbee). For networking and storage applications requiring much higher throughputs (40 Gbps, 100 Gbps and above), IP Cores, Inc. offers dedicated GCM and XTS core families. IP Cores, Inc. has also shipped a family of FFT DSP cores. Cores are available in multiple configurations to meet specific SoC throughput, power, and gate count goals. For more information about IP Cores’ product line, please visit www.ipcores.com.

About IP Cores, Inc.
IP Cores is a fast-moving company in the field of security and DSP IP cores. Founded 3 years ago, the company provides IP cores to protect communications, storage, and intellectual property.

IP Cores, Inc. announces three low-latency Fast Fourier Transform IP cores for SoC applications in the OFDM-based communications (WiMAX, MBOA, IEEE 802.11) and GPS fields. FFT64 core and two versions of FFT1024 are very compact and provide parameterized bit width with throughput of 1 sample per clock.

Palo Alto, California, June 19, 2007 -- IP Cores, Inc., expanding its portfolio beyond security IP cores, today announced three compact FFT IP cores to support OFDM-based communication standards like WiMAX, MBOA, IEEE 802.11. New FFT1024-4, FFT1024-8, and FFT64 IP cores enable System on Chip (SoC) vendors to design extremely compact OFDM modems.

"Addition of the FFT cores to our portfolio permits us to broaden our customer base," said Dmitri Varsanofiev, CTO of IP Cores. "The FFT cores offered by IP Cores, Inc. are extremely efficient and flexible. Their compact sizes are especially useful in WiMAX MIMO applications."

OFDM-Based Communication Standards

Practically every modern communication standard – from IEEE 802.11 wireless networks to satellite communications - relies on the orthogonal frequency division multiplexing (OFDM) technology. Transmission and reception of data using the OFDM modulation requires an implementation of the Fast Fourier Transform (FFT) and inverse FFT (IFFT) in the modem.

FFT1024 configurations support either a 1024 point complex FFT, IFFT or two 512 point simultaneous transforms, which is a useful feature for supporting the IEEE 802.16e (WiMAX) standard. Gate count for a fully self-contained 10-bit FFT1024-4 starts at 50K gates (the core also uses 40 Kbits of memory). FFT1024 is capable of processing one sample per clock at frequencies up to 250 MHz in the 90 nm ASIC process and 80 MHz in an FPGA. The latency of the FFT1024-8 is 420 clocks, while the smaller FFT1024-4 has a latency of 1260 clocks.

FFT64 core delivers the 64 point complex FFT used in IEEE 802.11 standard and GPS applications.

Cores are available in multiple configurations to meet specific SoC throughput, power, and gate count goals. For more information about IP Cores’ product line, please visit www.ipcores.com.

About IP Cores, Inc.
IP Cores is a rapidly growing company in the field of IP cores. Founded 3 years ago, the company provides IP cores for communications and storage fields. Security portfolio of IP Cores includes ultracompact AES core, multiple CCM cores supporting IEEE 802.11i (WiFi), IEEE 802.15.3 (UWB), WiMedia (MBOA), IEEE 802.15.4 (Zigbee), and IEEE 802.16e (WiMAX), storage security cores supporting AES-XTS mode, as well as multiple families of AES-GCM cores for MACsec (IEEE 802.1ae) and IPsec applications.

IP Cores, Inc. announces an FPGA implementation of the AES Galois/Counter Mode (GCM) supporting the IEEE 802.1ae standard with real-life throughput exceeding 10 Gbps for all Ethernet frame sizes.

Palo Alto, California, June 12, 2007 -- IP Cores, Inc. demonstrated the high throughput of its AES-GCM solutions by delivering an FPGA implementation of its GCM3 core that provides true 10 Gbps throughput for 10G Ethernet equipment for all Ethernet frame sizes.

"Delivery of a true 10 Gbps GCM3 core demonstrates our commitment to the high-speed FPGA implementations," said Dmitri Varsanofiev, CTO of IP Cores. "High-speed Ethernet equipment can now easily implement the line-speed IEEE 802.1ae encryption in an FPGA."

Line-speed Ethernet Encryption Standard Support
The IEEE 802.1ae encryption standard uses the Advanced Encryption Standard (AES) in the Galois/counter mode (GCM). For most Ethernet application, maintaining the line-speed throughput for all frame sizes is essential.

IP Cores, Inc. has designed the GCM2 and GCM3 families of the AES-GCM cores to maintain full-speed throughput for all Ethernet frame sizes. This allowed the cores to reliably deliver a line-speed 10 Gbps throughput using a Xilinx Vrtex-4 FPGA even for the shortest Ethernet frames. The ASIC implementations of the same cores deliver throughputs of 70 Gbps and beyond

GCM2 family of cores core is optimized to handle 128-bit keys, while GCM3 supports 128, 192, and 256 bit AES keys. Cores are available in multiple configurations to meet specific SoC throughput, power, and gate count goals. Gate count for a fully self-contained GCM2 or GCM3 core starts at 30K ASIC gates. For more information about IP Cores’ product line, please visit www.ipcores.com.

About IP Cores, Inc.
IP Cores is a rapidly growing company in the field of security IP cores. Founded 3 years ago, the company provides IP cores for encryption of communications and storage data.