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RSA Public Key Exponentiation Accelerator Core
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General Description |
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Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. |
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The operations necessary for the RSA cannot be efficiently implemented on an embedded CPU, however, typically requiring many seconds of the CPU time for signature verification. |
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RSA1-E implements by far the most time-consuming operation of the RSA cryptography: so called “exponentiation” to enable low-power operation of the battery-powered devices. |
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The design is fully synchronous and available in multiple configurations varying in bus widths, set of finite fields supported and throughput. |
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Key Features |
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Small size: RSA1-E starts from less than 10K ASIC gates (intermediate result storage memory required; size depends on the core configuration) |
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Implements the computationally demanding parts of RSA public key cryptography for long life battery powered applications |
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Support for RSA binary fields of configurable bit sizes up to 2048 |
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Microprocessor-friendly interface |
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Test bench provided |
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Applications |
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Secure communications systems |
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RFID |
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Implantable medical devices |
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Digital Rights Management (DRM) for battery powered electronics |
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Digital Signature using Reversible Public Key (rDSA) standard ANSI X9.31 |
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Digital Signature Standard (DSS) FIPS-186 |
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PKCS RSA cryptography per RFC 2347 |
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Pin Description |
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| CLK |
Input |
Core clock signal |
| CEN |
Input |
Synchronous enable signal. When LOW the core ignores all its inputs and all its outputs must be ignored. |
| RESET |
Input |
HIGH level asynchronously resets the core |
| READ |
Input |
Read signal for the interface |
| WRITE |
Input |
Write signal for the interface |
| DONE |
Output |
HIGH level indicates a completion of computation |
| D[ ] |
Input |
Input Data |
| A[ ] |
Input |
Address |
| Q[ ] |
Output |
Output Data |
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Function Description |
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| The core implements the exponentiation operation of the RSA cryptography Q = Pk. The operands for the exponentiation: k and P as well as the modulus are programmed through the microprocessor interface and the calculation is started. Once the operation is complete, the result Q can be read through the interface.
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Export Permits |
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| The core is subject to the US export regulations. See the IP Cores, Inc. licensing basics page,
for links to US government sites and more details. |
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Deliverables |
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HDL Source Licenses
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Synthesizable Verilog RTL source code |
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Software modules for a complete ECC implementation (optional) |
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Verilog testbench (self-checking) |
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Software modules test harness |
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Vectors for testbench and harness |
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Expected results |
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User Documentation
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Netlist Licenses
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Post-synthesis EDIF |
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Testbench (self-checking) |
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vectors for testbenches |
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Expected results |
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Contact Information |
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