RSA Public Key Exponentiation Accelerator IP Core

General Description

	Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”.
	The operations necessary for the RSA cannot be efficiently implemented on an embedded CPU, however, typically requiring many seconds of the CPU time for signature verification.
	RSA1-E implements by far the most time-consuming operation of the RSA cryptography: so called “exponentiation” to enable low-power operation of the battery-powered devices.
	The design is fully synchronous and available in multiple configurations varying in bus widths, set of finite fields supported and throughput.

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Key Features

	Small size: RSA1-E starts from less than 10K ASIC gates (intermediate result storage memory required; size depends on the core configuration)
	Implements the computationally demanding parts of RSA public key cryptography for long life battery powered applications
	Support for RSA binary fields of configurable bit sizes up to 2048
	Microprocessor-friendly interface
	Test bench provided

Applications

	Secure communications systems
	RFID
	Implantable medical devices
	Digital Rights Management (DRM) for battery powered electronics
	Digital Signature using Reversible Public Key (rDSA) standard ANSI X9.31
	Digital Signature Standard (DSS) FIPS-186
	PKCS RSA cryptography per RFC 2347

Pin Description

Name	Type	Description
CLK	Input	Core clock signal
CEN	Input	Synchronous enable signal. When LOW the core ignores all its inputs and all its outputs must be ignored.
RESET	Input	HIGH level asynchronously resets the core
READ	Input	Read signal for the interface
WRITE	Input	Write signal for the interface
DONE	Output	HIGH level indicates a completion of computation
D[ ]	Input	Input Data
A[ ]	Input	Address
Q[ ]	Output	Output Data

Function Description

The core implements the exponentiation operation of the RSA cryptography Q = Pk. The operands for the exponentiation: k and P as well as the modulus are programmed through the microprocessor interface and the calculation is started. Once the operation is complete, the result Q can be read through the interface.

IP Cores, Inc., 3731 Middlefield Rd., Palo Alto, CA 94303, USA

Phone: +1 (650) 815-7996 | E-mail: info@ipcores.com | www.ipcores.com