Home   About Us   News   Contact Us
RS100 Core. 100G Reed-Solomon Codec for Ethernet IEEE 802.3 Clause 91 (803.3bj)

General Description

The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 802.3bj (100G Backplane Ethernet) standard draft for 100GBASE-CR4 and 100GBASE-KR4 PHY. The encoder and decoder functions are completely independent and packaged as two sub-cores, RS100-160E and RS100-160D respectively. Decoder corrects up to 7 word errors; an option supporting RS(544, 514) for 100GBASE-KP4 PHY (correcting up to 15 errors) is also available .

Key Features

Implements FEC Sublayer for 100GBASE-CR4 and 100GBASE-KR4 PHY (clause 91 of the IEEE 802.3bj standard) 100G Ethernet MAC-friendly interface.

Core features include:

  • 160-bit parallel interface
  • Optional automatic FEC block boundary lock on decoding

Self-contained, requires no external memory. A reduced gate count version with a small external RAM is available.

Flow-through design; low latency




Pin Description

Name Type Description
clk Input Core clock signal
cen Input Synchronous enable signal. When LOW the core ignores all its inputs and all its outputs must be ignored.
reset Input Asynchronous reset
start Input HIGH pulse indicating the first word of the block
D[159:0] Input Input Data
Q[159:0] Output Output Data
strobe Output Cerr and NCerr outputs are valid
Cerr Output Error has been corrected
NCerr Output Uncorrectable errors detected

Function Description

The RS100-160E core implements the FEC encoder per section of the IEEE 802.3bj draft standard. The core accepts sixteen 10-bit words (160 bit total) on every clock and outputs the encoded result 3 clocks later.

The RS100-160D core implements the FEC decoder per section of the IEEE 802.3bj standard. It accepts sixteen 10-bit words (198 bit total) on every clock and outputs the decoded result 49 clocks later.